library IEEE;
use IEEE.std_logic_1164.all;

entity twoX16mux is
	port(A,B : in std_logic_vector(15 downto 0);
		output : out std_logic_vector(15 downto 0);
		sel : in std_logic);
end twoX16mux;

architecture logic of twoX16mux is
begin
	mux_gen : for i in 0 to 15 generate
		output(i) <= (A(i) and not sel) or (B(i) and sel);
	end generate;
end logic;

library IEEE;
use IEEE.std_logic_1164.all;

package mips_package2 is
	component twoX16mux
		port(A,B : in std_logic_vector(15 downto 0);
			output : out std_logic_vector(15 downto 0);
			sel : in std_logic);
	end component;
end mips_package2;
